1. Field
The present inventions relate to systems and methods of noise reduction and/or power saving, and, more specifically, to innovations consistent with delay lines in clock/timing circuits such as Delay-Lock-Loop (DLL) and/or Duty Cycle Correction (DCC) circuits.
2. Description of Related Information
Clock generators based on Delay-locked Loop (DLL) and Duty Cycle Correction (DCC) circuits can be used to change the on-chip internal clock phases. Here, for example, a DLL may align the rising edges of the internal clock signal with the external input clock, and a DCC may adjust the falling edges of the internal clock to have a desired (50%) duty cycle even when the external input clock does not have a 50% duty cycle. As such, a DLL/DCC-based clock generator can usually enhance the clock edge-to-data output valid timing characteristics of high speed integrated circuits such as Double-Data-Rate (DDR) DRAM and SRAM devices. In general, high speed and high performance DLL and DCC circuits are designed with a multiple of delay lines which consists of many delay cells in series and controlled by the outputs of shift registers. Such delay cells in the delay line can be built based either on a differential type for good power noise immunity or on the single-ended type for its low power consumption. Furthermore, the differential type delay cells are often used for high speed operation due to their small voltage swing, but these cells will consume a large amount of DC current. Each delay cell is controlled by the voltage output of a charge pump which has phase difference information between input reference clock and internal feedback clock.
For the differential type of delay cells and delay line, the circuitry needs to convert the clock signals from the differential output to the single-ended output or from the single-ended input to the differential input to communicate with the internal digital CMOS logics.
In order to save the locking time and to stabilize the internal clock generated from DLL or DCC, these delay lines typically must be made available right away when DLL and DCC are enabled. At that time, the DLL and/or DCC will demand a lot of power because conventionally all delay cells in the delay lines are made available for searching the digital locking position.
In addition, to address issues such as coverage of wider locking frequency ranges, the quantity of delay cells is increasing in accordance with the goal of achieving such wider frequency range(s). Moreover, in some existing implementations, un-used delay cells are often never switched off and/or not powered down. Indeed, inherent issues such as these may often mean that total current consumption of both DLL and DCC is increasing proportional to a total number of delay cells being used. As such, higher speed DLL and DCC designs typically consume more power than the lower speed DLL and DCC designs. Indeed, in high speed applications, each delay cell may easily consume a few hundred micro-amps (uA) of DC current or sometimes even more.
Existing systems sometimes use a method of turning on all delay cells at the same time in the delay lines of both DLL and DCC when they are activated to shorten the locking time and to stabilize the internal clock more quickly. However, doing so creates a large surge current which, in some applications, can be around a few hundred milliamps or larger. Such large peak current will make a correspondingly large voltage jump in the internal power supply as it attempts to supply such a large internal current instantly. Furthermore, the DLL and DCC are usually very sensitive to power supply fluctuations/noises. If the DLL and DCC see a large voltage jump on its power supply, it may take the DLL out of its locking state and create incorrect phase information for the whole chip.
For example, FIG. 1 depicts an existing illustration of a differential type delay line with a series of shift registers 120A, 120B, 120C, with Vdd input 134, and control waveforms 142, 132, 102, 148. Here, all the differential type delay cells 110A, 110B, 110C are turned on and wait for the control of the outputs of shifter registers to be selected. Behavior of the various signals show in the circuit, such as a clock signal (here, divided by 8) 130, up/down enable 132, and outputs of the shift registers (Q) 140A, 140B, 140C, is illustrated on the right side of FIG. 1 via waveforms including enable all cells 142, up/down enable 132, clock 102 and select (shift register output/Q) 148.
FIG. 2 illustrates some representative timing diagrams of the existing design shown in FIG. 1. Illustrated from top to bottom in FIG. 2 are enable all cells 153, clock 150, up/down enable 151, first through fourth select lines 152, 154, 156, 158, total current 162 and chip power supply 170. Before the phase-locking condition is achieved, all the registers 120 of the shift register are turned on, as shown in the drawing via the enable all cells signal 153. This corresponds to a jump 164 in the total current. Then, after a phase-lock condition occurs, the unused delay cells are turned off, i.e., once at lock 160, to save power 166. Accordingly, such circuits may create large current jump or spike 168 with the adverse effects of supply voltage dropping 172, then jumping up 174 and dropping down 176, creating fluctuations in internal chip power supply 170.
Accordingly, because of fluctuations such as these, chips often need to have numerous very wide power buses and also a large amount of de-coupling capacitors to stabilize its internal clock signal. These additional circuits demand more silicon area and thus adversely increase the overall cost of the integrated circuits.